How do I use the channel_reset port in the 25G Ethernet Intel® Stratix® 10 FPGA IP?

Description

Due to a mistake in the UG-20109 | 2020.04.13, there is no description of channel_reset port for 25G Ethernet Intel® Stratix® 10 FPGA IP. The channel_reset port is a reset input that is only present if the Enable 10G/25G Dynamic Rate Switching option is checked. Before initiating reconfiguration between speeds, assert this signal to hold the TX/RX data paths in reset. 

Resolution

This missing information has been added in UG-20109 | 2020.07.29.