How do I prevent PLL output counter merging in Quartus® II 12.1 and later for Intel® Stratix®, Arria® V and Cyclone® V FPGA devices?

Description

In Quartus® II versions 12.1 and later, you can use the QSF variable UNFORCE_MERGE_PLL_OUTPUT_COUNTER to prevent the PLL output counters from merging in Stratix® V, Arria® V, or Cyclone® V devices.

Resolution

Below is an example of the assignment being made to a PLL output counter:

set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "mypll:inst|mypll_0002:mypll_inst|altera_pll:altera_pll_i*”

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