How can the data stored in the read data FIFO in the Stratix® 10 FPGA Serial Flash Mailbox Client IP core be read with a JTAG host?

Description

The read data FIFO can be accessed through the “rd_mem” bus in the Stratix® 10 FPGA Serial Flash Mailbox Client IP core. To read the data stored in the read data FIFO, you need to read data from the “rd_mem” bus. Refer to the IP rd_mem’s base and end address in the Platform Designer for the start address and the list of addresses you can read.

For more details about the read operation flow, refer to the Stratix® 10 FPGA Serial Flash Mailbox Client IP Core User Guide.

Resolution

For more details about the read operation flow, refer to the Stratix® 10 FPGA Serial Flash Mailbox Client IP Core User Guide.