Error (178004): Could not find location for Clock Divider that enable routing of bonding clock lines

Description

You may see the following Quartus® II Fitter error with Stratix® V GX and Arria® V GX devices if you attempt to place logical channel 0 of a bonded transceiver PHY IP on a transceiver channel that does not have access to a central clock divider block.

"Error (178004): Could not find location for Clock Divider that enable routing of bonding clock lines"

On Stratix V and Arria V transceiver devices, only physical channels 1 and 4 within a transceiver block can access a central clock divider.

Resolution

To work around this problem, assign logical channel 0 of the PHY IP to physical channel 1 or 4 of the transceiver bank.

This information will be updated in a future version of the Altera Transceiver PHY IP Core User Guide.

This limitation was removed in version 11.1.1 of the Quartus® II software.