Do the ATX PLL spacing requirements apply when using configuration profiles in the ATX PLL IP with Arria® 10 devices?

Description

Yes, the ATX PLL spacing requirements apply when using configuration profiles in the ATX PLL IP with Arria® 10 devices.

Resolution

If your ATX PLL IP and FPLL IP components use the configuration profile feature to reconfigure to different datarates, you must manually check that the spacing requirement is met for all configuration profile combinations.

A critical warning should be produced by the Quartus® Prime software when the ATX PLL to ATX PLL or ATX PLL to FPLL spacing requirement is violated. An example critical warning is below.

Critical Warning(18499): ATX PLL <Gen_LHDx0.LHDx1|Gen_ATXPLL.Gen_ATXUSR0.ATXPLL_i0|xcvr_atx_pll_a10_0|atx_pll_inst> are too close to ATX PLL <Gen_LHDx1.LHDx1|Gen_ATXPLL.Gen_ATXUSR1.ATXPLL_i0|xcvr_atx_pll_a10_0|atx_pll_inst>. For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs apart.

However in the example below, no critical warning will be produced by the Quartus® Prime software.

ATXPLL constrained to location HSSIPMALCPLL_1CB

Profile 0 = 10G3 (Default at compile time)

Profile 1 = 12G5

ATXPLL constrained to location HSSIPMALCPLL_1CT

Profile 0 = 10G3

Profile 1 = 12G5 (Default at compile time)

The Arria® 10 ATX PLL to ATX PLL, and ATX PLL to fPLL spacing requirement is documented in the “3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs” section of the Arria® 10 Transceiver PHY IP userguide.