Why are the propagation delays simulated by my Quartus software clearly wrong?
I've designed a circuit of 39 two-input AND gates. The output of the previous feeds into one of the input of the next, and the second input has a logic '1' always at the input. I then use a waveform ...
How did you select those signal gd[x] in the simulation? Are all of gd[X] are connected to IO port? Can upload tech map viewer for that implementation?