Forum Discussion
DWels3
New Contributor
New ContributorWhy are the propagation delays simulated by my Quartus software clearly wrong?
I've designed a circuit of 39 two-input AND gates. The output of the previous feeds into one of the input of the next, and the second input has a logic '1' always at the input. I then use a waveform ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi DWels 3,
Referring to https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html
Gate level timing is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.
Thanks.
