Altera_Forum
Honored Contributor
9 years agoVideo IP - simple test vga interface
Hi there,
I am attempting to create a simple Qsys system that can stream data over out over a video connection. I have decided to use the VGA interface available on the DE1-SoC boards. Eventually I want to be able to use the Qsys design to stream data out that is stored on the SDRAM of the dev kit. However I am getting stuck just getting the VGA working! I have found a video test pattern generator, an rgb resampler, the dual clock FIFO and the VGA controller but when I connect everything up and generate the Qsys system and programme it to the board, I only get a black screen for the output. Can anyone tell me where I am going wrong? (I have attached some screen shots) http://www.alteraforum.com/forum/attachment.php?attachmentid=12725&stc=1
SDRAM u0 (
.clk_clk (CLOCK_50), // clk.clk
.reset_reset_n (KEY), // reset.reset_n
.wire_addr (DRAM_ADDR), // wire.addr
.wire_ba (DRAM_BA), // .ba
.wire_cas_n (DRAM_CAS_N), // .cas_n
.wire_cke (DRAM_CKE), // .cke
.wire_cs_n (DRAM_CS_N), // .cs_n
.wire_dq (DRAM_DQ), // .dq
.wire_dqm ({DRAM_UDQM, DRAM_LDQM}),// .dqm
.wire_ras_n (DRAM_RAS_N), // .ras_n
.wire_we_n (DRAM_WE_N), // .we_n
.sdram_clk_clk (DRAM_CLK), // sdram_clk.clk
.vga_CLK (VGA_CLK), // vga.CLK
.vga_HS (VGA_HS), // .HS
.vga_VS (VGA_VS), // .VS
.vga_BLANK (VGA_BLANK), // .BLANK
.vga_SYNC (VGA_SYNC), // .SYNC
.vga_R (VGA_R), // .R
.vga_G (VGA_G), // .G
.vga_B (VGA_B) // .B
);
assign VGA_BLANK_N = ~VGA_BLANK;
assign VGA_SYNC_N = ~VGA_SYNC;
cheers