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Altera_Forum's avatar
Altera_Forum
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15 years ago

vhdl stopwatch with LPM RAM

Hi, I am doing a lab assignment about a VHDL stopwatch. this watch can store 16 32-bits timestamp in the memory. and when readmode = '1', the stopwatch will show the timestamps. below i...
Altera_Forum's avatar
Altera_Forum
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15 years ago

First problem I see: 


------------------------reset Memory------------------------
    for i in 0 to 15 loop
     addr <= r_counter;
     r_counter := r_counter + 1;
    end loop;

Your address actually increments by 16 on each clock, so the addresses in between are not written to.

Also, you have included std_logic_unsigned and numeric_std. You should only use one or the other - (numeric_std is a standard package, std_logic_unsigned is not an IEEE standard).

Did you have any problems other than these?