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Wcheekei's avatar
Wcheekei
Icon for New Contributor rankNew Contributor
3 years ago
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VHDL code for JK flip-flop issue

Hi, I'm having issue trying to understand the code generated by the software Intel Quartus Prime. The JK flip-flop block used has an IF-ELSE statement that conflicts with each other. The SYNTHESIZED...
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  • FvM's avatar
    FvM
    3 years ago
    Hello,
    synthesized code is often not well readable. The strange SYNTHESIZED_WIRE_2 coding is produced by connecting set and reset inputs together in your schematic input. Nevertheless it's logically correct.

    Most recent FPGA families don't support simultaneous usage of asynchronous set and reset, you should avoid it in code intended for FPGA synthesis.
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed. Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day!


Best Regards,

Richard Tan