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Wcheekei's avatar
Wcheekei
Icon for New Contributor rankNew Contributor
3 years ago
Solved

VHDL code for JK flip-flop issue

Hi, I'm having issue trying to understand the code generated by the software Intel Quartus Prime. The JK flip-flop block used has an IF-ELSE statement that conflicts with each other. The SYNTHESIZED...
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  • FvM's avatar
    FvM
    3 years ago
    Hello,
    synthesized code is often not well readable. The strange SYNTHESIZED_WIRE_2 coding is produced by connecting set and reset inputs together in your schematic input. Nevertheless it's logically correct.

    Most recent FPGA families don't support simultaneous usage of asynchronous set and reset, you should avoid it in code intended for FPGA synthesis.
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Yes, he is right. To add-on, asynchronous set and reset signals are not synchronized to the clock and can introduce timing hazards and metastability issues. The simultaneous use of asynchronous set and reset signals in a flip-flop can lead to race conditions, data instability, and unpredictable behavior, making it difficult to meet timing requirements and ensure reliable operation.

You may checkout this document for further details.

https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/asynchronous-design-hazards.html

We recommend that users to follow the Synchronous FPGA Design Practices.


Best Regards,

Richard Tan


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