VGA VHDL DE2 problem

Hi hencel,

I tried to make the vhdl code to work, but there is a tiny flaw in the code. When I checked my signals with an oscilloscope or with my simulation, it looked like it should work. After a while I decided to learn verilog because it is very hard to keep vhdl compact. Verilog might be a bit harder but if you can read it it's much more convenient (well-organized). If you only know VHDL you could try to alter my code in the first post, I only have a working verilog driver.

There are a lot of universities who use the de2 board, if you check their websites there are lots of examples how to use VGA in both verilog and VHDL.

If you dont know how VGA works, you could check:

http://www.epanorama.net/documents/pc/vga_timing.html

For the list of links of universities:

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=39&no=30

This link helped me a lot:

http://www1.cs.columbia.edu/~sedwards/classes/2007/4840/video.pdf (http://www1.cs.columbia.edu/%7esedwards/classes/2007/4840/video.pdf)

-Roelof