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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Verilog FSM stuck on one State forever

I am developing a fsm to latch on to incoming data and compute its average in verilog, but my fsm seems to be just stuck at one state. Although the simulation shows it did shifted perfectly in previ...
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  • RichardT_altera's avatar
    RichardT_altera
    1 year ago

    You have nextstate in your case statement, but state never updates to nextstate.

    Fix it by adding a sequential block to update state at every clock edge.

    always @(posedge clk) begin
      if (~rst)
        state <= idle;
      else
        state <= nextstate;
    end

    I would recommend to checkout 'Two Always Block FSM coding style' from the article below.

    It uses two separate always blocks:

    1. State Register Block: A sequential (always_ff ) block that updates the current state (state_reg) on the clock edge.
    2. Next State & Output Logic Block: A combinational (always_comb) block that determines the next state and the outputs based on the current state and inputs.

    http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

You have nextstate in your case statement, but state never updates to nextstate.

Fix it by adding a sequential block to update state at every clock edge.

always @(posedge clk) begin
  if (~rst)
    state <= idle;
  else
    state <= nextstate;
end

I would recommend to checkout 'Two Always Block FSM coding style' from the article below.

It uses two separate always blocks:

  1. State Register Block: A sequential (always_ff ) block that updates the current state (state_reg) on the clock edge.
  2. Next State & Output Logic Block: A combinational (always_comb) block that determines the next state and the outputs based on the current state and inputs.

http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf

Regards,

Richard Tan

  • Fpga_Egr_2025's avatar
    Fpga_Egr_2025
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    HI Richard,

    Yes changed the fsm to have two separate always block :

    ////////////////////////////////////
    always @ (posedge clk) begin
    if (~rst) begin
    state <= idle;end
    else begin
    state <= nextstate;end
    end
    ////////////////////////////////////
    always @(*) begin
    nextstate <= idle;
    case(state)
    idle:begin
    if(vld)begin
    rdy_sig <= 1'b1;
    nextstate <= buffer_data;
    end
    else if (last)begin
    rdy_sig <= 1'b0;
    valid_no_reg <= valid_no;
    nextstate <= filter_data_state;end