Verilog FSM stuck on one State forever

You have nextstate in your case statement, but state never updates to nextstate.

Fix it by adding a sequential block to update state at every clock edge.

always @(posedge clk) begin
  if (~rst)
    state <= idle;
  else
    state <= nextstate;
end

I would recommend to checkout 'Two Always Block FSM coding style' from the article below.

It uses two separate always blocks:

1. State Register Block: A sequential (always_ff ) block that updates the current state (state_reg) on the clock edge.
2. Next State & Output Logic Block: A combinational (always_comb) block that determines the next state and the outputs based on the current state and inputs.

http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf

Regards,

Richard Tan