Forum Discussion
SyafieqS
Super Contributor
2 years agoThere is no template Verilog for serial communication, we used IP that is integrated in Qsys, generated to HDL.
You can use that way.
snehalatha
New Contributor
2 years agoThanks for your replay!!!
Can we implement UART with Avalon mm interface without Nios II or any other processors??