Verilog code for a clock

Have you simulated your design? If you have, you would easily see the problem.

I can't match your code with what you describe.

As I understand, CLK is the hour clock, and you want to use this clock to count from 0 to 12 in a BCD sequence and display the result on two 7-segment LEDs as the hour, right?

I would do it as the following:

module decimal_counter_20(A,B,CLK,RST);

input CLK, RST;

output [3:0] A; // suppose A is the higher digit of hour counter

output [3:0] B; // suppose B is the lower digit of hour counter

reg [4:0] C; // hour counter from 0 ("00000")to 12 ("10010") in BCD sequence

always @ (posedge CLK or negedge RST)

if (~RST)

C <= 5'b00000;

else

if (C == 5'b10010)// count to 12, reset to 0

C <= 5'b00000;

else

if(C[3:0] == 4'b1001) //when lower digit reaches 9

begin

C[3:0] <= 4'b0000; //lower digit resets to 0

C[4] <= 1'b1; //higher digit becomes 1

end

else

C[3:0] <= C[3:0] + 4'b1; // increase by 1

//assign the lower digit of counter to B

assign B = C[3:0];

//A can only be either 0 or 1, so A[3:1] are always 0

assign A[0] = C[4];

assign A[3:1] = 3'b000;

endmodule