Honored Contributor
Honored ContributorAlong with the prior post information (all good points) be aware that the FPGA device on the boards is a different generation, going from Cyclone II on DE2 to Cyclone IV on DE2-115. So typically any instantiations of Altera specific modules in your verilog (PLL clock generators, memory arrays, any IP blocks) may also have to be modified. Vanilla verilog code that is being synthesized is usually not an issue, Quartus will take care of that.
Altera DE2 Board : Cyclone II EP2C35F672 with ~35,000 LEs Altera DE2-115 Board : Cyclone IV EP4CE115 with ~114,480 LEs
