University Program IP Cores and Quartus II 7.2

Hi !

I have used VGA Core but I don't control VGA monitor. can you help me?

module vgacontroller ( KEY, CLOCK_50, DRAM_CLK, DRAM_CKE,

DRAM_ADDR, DRAM_BA_1, DRAM_BA_0, DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N,

DRAM_WE_N, DRAM_DQ, DRAM_UDQM, DRAM_LDQM,

SRAM_ADDR,

SRAM_CE_N,

SRAM_DQ,

SRAM_LB_N,

SRAM_OE_N,

SRAM_UB_N,

SRAM_WE_N,

//////////////////// VGA ////////////////////////////

VGA_CLK, // VGA Clock

VGA_HS, // VGA H_SYNC

VGA_VS, // VGA V_SYNC

VGA_BLANK, // VGA BLANK

VGA_SYNC, // VGA SYNC

VGA_R, // VGA Red[9:0]

VGA_G, // VGA Green[9:0]

VGA_B, // VGA Blue[9:0]

);

input [0:0] KEY;

input CLOCK_50;

output [11:0] DRAM_ADDR;

output DRAM_BA_1, DRAM_BA_0, DRAM_CAS_N, DRAM_RAS_N, DRAM_CLK;

output DRAM_CKE, DRAM_CS_N, DRAM_WE_N, DRAM_UDQM, DRAM_LDQM;

inout [15:0] DRAM_DQ;

wire CLOCK_25;

inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits

output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits

output SRAM_UB_N; // SRAM Low-byte Data Mask

output SRAM_LB_N; // SRAM High-byte Data Mask

output SRAM_WE_N; // SRAM Write Enable

output SRAM_CE_N; // SRAM Chip Enable

output SRAM_OE_N;

//////////////////////// VGA ////////////////////////////

output VGA_CLK; // VGA Clock

output VGA_HS; // VGA H_SYNC

output VGA_VS; // VGA V_SYNC

output VGA_BLANK; // VGA BLANK

output VGA_SYNC; // VGA SYNC

output [9:0] VGA_R; // VGA Red[9:0]

output [9:0] VGA_G; // VGA Green[9:0]

output [9:0] VGA_B; // VGA Blue[9:0]

// Instantiate the Nios II system module generated by the SOPC Builder

nios_system NiosII (

CLOCK_50,

CLOCK_25,

KEY[0],

DRAM_ADDR,

{DRAM_BA_1, DRAM_BA_0},

DRAM_CAS_N,

DRAM_CKE,

DRAM_CS_N,

DRAM_DQ,

{DRAM_UDQM, DRAM_LDQM},

DRAM_RAS_N,

DRAM_WE_N,

SRAM_ADDR,

SRAM_CE_N,

SRAM_DQ,

SRAM_LB_N,

SRAM_OE_N,

SRAM_UB_N,

SRAM_WE_N,

VGA_BLANK,

VGA_B,

VGA_G,

VGA_HS,

VGA_R,

VGA_SYNC,

VGA_VS

);

// Instantiate the module sdram_pll (inclk0, c0)

sdram_pll neg_3ns (CLOCK_50, DRAM_CLK,CLOCK_25,VGA_CLK);

endmodule

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