--- Quote Start ---
This is not a bug. The DE External Interface core no longer creates the extra clock, since the VGA core no longer requires it. There was an issue with the VGA core while passing data from the 50MHz clock domain to the 25MHz clock domain. Now the VGA core only using the 50MHz clock domain, but a 25MHz clock is still needed to be sent to the VGA chip via the VGA_CLK pin.
--- Quote End ---
So I need the make a 25 MHz clk with a PLL and connect it to the VGA_CLK pin?
And if I'm using the SDRAM module I have also a problem with the clk. The SDRAM also needs a special clk, but the DE External Interface core don't add the extra clk. But a extra signal used by shown in the Clock section in the top-right corner of the SOPC Builder. Those the DE External Interface core no longer creates this extra clock?
Honored Contributor
