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Sorry，when i debug my FPGA，i only use one ethernet interface that listening to my
fpga.So what is the different between direct use of cable and USB-Ethernet adapter。Thank you!
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I guess I was recommending a way to separate the device under test from all other Ethernet traffic on your PC. I found that my laptop is generating traffic on the default NIC. Having the adapter helped me have an isolated ethernet interface that my CPU doesn't use for anything. So the only traffic I see is what I send out that port, and what comes back. But I'm a noob with wireshark, so this was a simple and inexpensive trick to help me get there. It sounds like this is not a solution to your problem.
If the interface is not a problem and you know it's RGMII coming out, then you might look into your Ethernet headers to see if you are byte-ordering them correctly in the packet. If unsure, look at the way the Altera testbench inserts the mac address into the octet stream. At first I did not see anything in wireshark until I re-ordered the bytes. Also turn on 'promiscuous mode' in wireshark capture options if you haven't done this already.
Otherwise please state the problem more clearly, what you've tried and what didn't work, how it looked in the simulation, etc. to get more refined answers.
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