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In order to troubleshoot this, we assigned the SCLK and SDAT to two GPIO pins, and analyzed the result with a logic analyzer. The pins seem to be driven high ar all times, and no data sequence or clock is seen.
Here comes the funny part. Given the pull-up nature of the I2C bus as well as the GPIO pins, we are writing 'Z' to the pin when we want it to be high, and '0' when we want it to be low, using std_logic. And as I explained before, this only results in a constant high value of SCLK and SDAT. However, if we use '1' and '0' for high and low respectively, everything seems to be fine on the logic analyzer.
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Do you mind posting the related HDL code?
Please also check the i2c signals are being assigned to the correct fpga pins
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