Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI emailed terasic support and the problem appears to be when using a updated version of quartus.
The original project was created on Quartus 9.0 and i'm compiling with 10.1sp1. So in the end the solution is: --- Quote Start --- We have to create the clock for D5M_PIXLCLK manually for this demo, please open the DE2_115_D5M_VGA.sdc file and insert the command "create_clock -period 30.0 [get_ports D5M_PIXLCLK]" into Create Clock as shown --- Quote End --- See the screen shot. this fixed it for me, but they also said this: --- Quote Start --- You can adjust the D5M_PIXLCLK data until you get the correct output, D5M CCD Input clock frequency is about 25Mhz --- Quote End ---