New Contributor
ContributorIf you wanted to build a sequential case statement in VHDL, the clock event has to put outside of case. Check an example of state machine https://www.intel.com/content/www/us/en/programmable/quartushelp/15.0/mergedProjects/hdl/vhdl/vhdl_pro_state_machines.htm. To compile it, revise the coding as follow:
if (clk'event and clk='1') then
case x is
when 0 => ---- there is my error occured
if y/=(Ts/2)then carrier <=y+1; y<=y+1;
else x<=1;carrier<=y-1;y<=y-1;
end if;
end if;
when 1 =>
if y/=0then carrier <=y-1; y<=y-1;
else x<=0;carrier <=y+1; y<=y+1;
.............
end if;
New Contributoror can i change the code like this
is this same meaning of my code?
architecture Behavioral of triangular_carrier is
signal x,y:INTEGER:=0;
begin
process(clk,Ts)
begin
case x is
when 0 =>if (clk='1') then
if y/=(Ts/2)then carrier <=y+1; y<=y+1;
else x<=1;carrier<=y-1;y<=y-1;
end if;
end if;
when 1 =>if (clk='1') then
if y/=0 then carrier <=y-1; y<=y-1;
else x<=0;carrier <=y+1; y<=y+1;
end if ;
end if;
when others=>null;
end case;
end process;
end Behavioral;
