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Altera_Forum's avatar
Altera_Forum
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17 years ago

synthesis question

Hi, I don't have access to synthesis tools at the moment and I am confused how this would synthesize: always @(posedge clk) if (rst) valid <= 0; else be...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks GPK. I plan to download the software.

Can you post a text file of the gate netlist?

Thanks again.