There are no generic ports in this file, and all component ports have an instantiated port map, though the signal names don't match exactly. For example, here's the LCELL component and its instantiation:
COMPONENT LCELL
PORT (
a_in : IN STD_LOGIC;
a_out : OUT STD_LOGIC);
END COMPONENT;
-- This creates, using iteration, a chain of LCELL buffers for each A, B, C, D signal,
-- which act to delay the signals.
LCA_1: LCELL PORT MAP(a_in=> A, a_out=>A_internal(0));
Gen_delay_A : FOR i in 0 to 23 GENERATE
LC : LCELL PORT MAP(a_in => A_internal(i), a_out => A_internal(i+1));
END GENERATE;
LCB_1: LCELL PORT MAP(a_in=> B, a_out=>B_internal(0));
Gen_delay_B : FOR i in 0 to 23 GENERATE
LC : LCELL PORT MAP(a_in => B_internal(i), a_out => B_internal(i+1));
END GENERATE;
LCC_1: LCELL PORT MAP(a_in=> C, a_out => C_internal(0));
Gen_delay_C : FOR i in 0 to 23 GENERATE
LC : LCELL PORT MAP(a_in => C_internal(i), a_out => C_internal(i+1));
END GENERATE;
LCD_1: LCELL PORT MAP(a_in=> D, a_out => D_internal(0));
Gen_delay_D : FOR i in 0 to 23 GENERATE
LC : LCELL PORT MAP(a_in => D_internal(i), a_out => D_internal(i+1));
END GENERATE;
As for the component files, whenever I add a file to the project, the only folder it allows me to add it to is the "Top Level" folder, I don't know if that's significant.
The attached file is the (actual) top level code. Thanks again.
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