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Lily1234's avatar
Lily1234
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4 years ago
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Stratix10 FPGA PAM4 signal

Hi all, I am doing some research of PAM4 receiver. From the file of doucment of Stratix10 E-tlie transceiver PHY user guide, I still have one question want to confirm, could you please give me so...
  • CheepinC_altera's avatar
    CheepinC_altera
    4 years ago

    Hi Lily,


    As I understand it, you have some inquiries related to the S10 E-Tile trasnceiver. For your information, the S10 E-Tile Receiver support data rate up to 57.8Gbps for PAM4 mode. The LVPECL is the IO standard selected but as for the receiver specs, you should refer to the E-Tile datasheet.


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin


Lily1234's avatar
Lily1234
Icon for New Contributor rankNew Contributor
4 years ago

Hi Chee,

Sorry for the late response, I really appreciate your kindly reply. But i still feel confused about how to process PAM4 signal.

For the I/O standard LVPECL, it used to receive PAM4. Does it have any demand for PAM4 EYE(like noise, three eye width and eye height)?

If there are have any document about PMA4 test result in the FPGA? I think it will be very useful to us to understand the question.

Thanks again ! Looking forward for you reply.

Best regards,

Lily