New ContributorStratix10 FPGA PAM4 signal
Hi all,
I am doing some research of PAM4 receiver. From the file of doucment of Stratix10 E-tlie transceiver PHY user guide, I still have one question want to confirm, could you please give me some suggesstion?
For the PAM4 signal, I/O standard is LVPECL, I am very confused, LVPECL is used for coms, that means after LVPECL, the output is 0 or 1. If it is possible ro send a 20G analog PAM4 signal to this FPGA?
Below is the the stratix 10 doucment I used. Please see the page67, present the E-TILE receiver specifications.
Thank you so much!
Lily
Hi Lily,
As I understand it, you have some inquiries related to the S10 E-Tile trasnceiver. For your information, the S10 E-Tile Receiver support data rate up to 57.8Gbps for PAM4 mode. The LVPECL is the IO standard selected but as for the receiver specs, you should refer to the E-Tile datasheet.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
