Forum Discussion
stratix 10dx PCIe gold finger recognition
- 3 years ago
Hi,
I am not sure what you had modified.
But I suggest you to look back the design, ensure all pin is connected in what the IP suggested.
Regards,
Wincent_Intel
Hi,
As long as the slot of the Host PC can support the desired PCie gen speed,
then it should be able to at least detect the FPGA’s PCIe interface (provided it can link up correctly).
Did you try to program any .sof file yet ?
If not I suggest you to try to generate one from the Quartus "IP catalog"
Also, You may try the same with different PC/server/slots to isolate if there is any dependency, and then you can also compare the BIOS setting for any difference.
Regards,
Wincent_Intel
- EastGun-A3 years ago
New Contributor
I changed the sof file to pof and proceeded with programming.
Well, while modifying the pcie example, slack got -88, so I wonder if this is why it is not recognized.
Although the link up has been completed, I have confirmed that the completion TLP of the configuration read does not return, so I wonder if it is a problem caused by slack (setup/hold time violation).- Wincent_Altera3 years ago
Regular Contributor
Hi,
- Do the error happen while you program the .sof file as well ?
- Do the TLP configuration read able to complete without modifiying anything ?
- What is the LTSSM status ? is it in L0 stage ?
- Can you show the printscreen error of slack -88 ?
Regards
Wincent_Intel
- EastGun-A3 years ago
New Contributor
Well, I couldn't attach the file now (I haven't received the detailed LTSSM status and file yet), but TLP communicated normally before the fix.
The sof file was also programmed normally. (both before and after TLP correction)thank you always.