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Altera_Forum's avatar
Altera_Forum
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14 years ago

simulate simple traffic light example (VHDL, DE2)

Hi, i wrote a simple VHDL traffic light program using a clock divider to get a 1hz clock which i think is helpfull. clockdivider: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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The waveform will be generated in the simulator, but you still need to generate a clock and reset, and this is where the testbench comes in,

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ah okay .. so i can't just simulate the board inputs and the 50 mhz clock, which is hardwired on the altera de2?

again thx for the quick answer