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Altera_Forum
Honored Contributor
14 years agosimulate simple traffic light example (VHDL, DE2)
Hi, i wrote a simple VHDL traffic light program using a clock divider to get a 1hz clock which i think is helpfull. clockdivider: library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.S...
Altera_Forum
Honored Contributor
14 years agothx again,
i don't know if a testbench is what i'm looking for. i need some kind of waveform , which shows the output signals + time dependency and i'm trying to get an 1hz clock ... will this be possible with my approach?