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Altera_Forum
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14 years ago

simulate simple traffic light example (VHDL, DE2)

Hi, i wrote a simple VHDL traffic light program using a clock divider to get a 1hz clock which i think is helpfull. clockdivider: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.S...
Altera_Forum's avatar
Altera_Forum
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14 years ago

To do both, you will need to create a testbench. A testbench is behavioural code that you do not compile in quartus - you use a simulation tool like modelsim. In it, you instantiate the unit under test (UUT) and drive the inputs and monitor the outputs. You can even read and write to text files if you want.