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Altera_Forum
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17 years ago

Simple Verilog Question

Hello I am trying to make a simple multiplexer on the de2-70. I know there are many ways to do this but I was wondering why the following code does not do the task. Task: Read switch 17 if switch ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

sanmaro ist correct, this is a pitfall and sometimes hard to find but if you write it as suggested

assign oLEDR = iSW[17] ? iSW[15:8] : iSW[7:0];

then is clear and easy to read and of course to check.

but be aware of glitches as you only do combinatorical logic

if possible better use a clock and registers for the output.

declare oLEDR as a wire, add a register like

reg [7:0] MyReg;

always @ ( posedge MyClock )

MyReg <= iSW[17] ? iSW[15:8] : iSW[7:0];

and then assign the register to the output

assign oLEDR = MyReg;