Simple Verilog Question

Hi Blue1440,

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I know this is simple...but I am really just confused on the vector sintax. I would like to understand it better, so if anyone can fix the code or point me to a good tutorial on vector notation I would really appreciate it.

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In the Verilog code that you write, you use the Verilog "&" and "|" bitwise operators. They operate on corresponding bits in the vector(s) of the two operands, starting from the least significant bit.

When you write:

~iSW&iSW

this means that the first vector is ~iSW[17] and the second vector is iSW[7:0]. When doing bitwise "&" it means that ~iSW[17] is ANDed ONLY with bit iSW[0]. So you should eather make a bit extension to your condition for switch 17 for example as:

{~iSW,~iSW, ~iSW,~iSW,~iSW,~iSW,~iSW,~iSW}&iSW

or better use the inline if-then-else "? :" construct as given below:

module Lab1 (iSW, oLEDR);
  input iSW;
  output oLEDR;
 
  assign oLEDR = iSW ? iSW : iSW;
 
endmodule

Hope this helps!