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Just a couple of responses to your questions.
Congratulations "cafukarfoo". You are definately are on the right track. The fact your DE2 board is acquiring an IP over DHCP means the ethernet connection is up and operational. Remember...you can only telnet into the board when a server socket is setup and listening on a particular protocol/port. Try testing your SSS by pinging the DE2 board. If the board reply's to a ICMP packet (ping), then everthing is working and ready for you to implement socket comms.
Well done also to "shenlung". I believe you can access the link status through a memory register on the Davicom DM9000A controller device. You will need to check the datasheet and modify the ethernet driver accordingly.
A few notes also to those who have asked:
- Yes, project was build on Quartus Web edition.
- Once running, found the SSS to be extremely stable. Wrote a C library to facilitate socket comms between the DE2 and a Win32 console app. Found the link to be stable and capable of transferring a large amount of data between the DE2<-->PC with no errors.
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Good day tnndesign thanks for your comment. I did not implement as part of driver, I implemented a task to read the PHY. This worked except occasionally would lock up the socket communication, I initially had the task priority at a lower number than the simple socket server task, but it occurred to me perhaps the PHY task was being executed mid low level driver activity, mucking up the driver, so I changed the task priority number above the SSS task. It now appears to work but I will test it more. This obviously is not implemented at the driver level but I would like to do so as you suggested. What is involved to implement at the driver level yet keep the function from clobbering the socket communication.
Thanks
shenlung
# define LINK_DOWN ((Enables & 0xc) | 0x1)
# define LINK_UP ((Enables & 0xc) | 0x2)
void SSSMonitorPhyTask(void *task_data)
{
INT16U status;
int disconnect_count;
int data;
int Enables;
disconnect_count=0;
while(1)
{
/* Run task once a second */
OSTimeDlyHMSM(0,0,1,0);
/* Read PHY */
data = 0x41; /* PHY Regester offset into EPAR Bit 4..0, PHY address into EPAR Bit 7..6 */
dm9000a_iow(0xC, data); /* write to dm9000a */
usleep(5); /* 5uS max delay */
data = 0x0c; /* Write 0x0c into EPCR reg 0x08 to start PHY + READ operation */
dm9000a_iow(0xb, data);
usleep(5);
data = 0x08; /* Write 0x08 into EPCR reg 0x0b to clear READ command */
dm9000a_iow(0xb, data);
usleep(5);
status = dm9000a_ior(0xd); /* Read PHY low byte from EPDRL reg */
printf("\n%x\n", status);
if(!(status & 0x4)) //Link Down set front panel LED red
{
Enables = IORD_ALTERA_AVALON_PIO_DATA(PIO_ENABLES_BASE);
/* Set BiColor LED red */
IOWR_ALTERA_AVALON_PIO_DATA(PIO_ENABLES_BASE, LINK_DOWN);
disconnect_count++;
if(disconnect_count > MAX_CABLE_DOWN )
{
printf("\nPHY ERROR: Ethernet Cable Disconnected!\n");
}
}
else // Link Good set front panel LED Green
{
Enables = IORD_ALTERA_AVALON_PIO_DATA(PIO_ENABLES_BASE);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_ENABLES_BASE, LINK_UP);
}
}
}
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