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Honored Contributor
Honored ContributorSimple Socket Server on DE2 w/Davicom DM9000A
updated. Altera's Simple Socket Server demo running on a DE2 board with the Davicom DM9000a driver. here it is....zipped downloaded project source for sss on the de2 board. download link c...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ok i get this message every time i try to run the programm --- Quote End --- Certainly unusual. If I didn't know better, would say this is a timing issue, but as long as you are using the SOF file in the Quartus directory you shouldn't be having any trouble. Program memory is set to the SDRAM chip which requires a PLL to compensate for clock skew (approx -3ns shift). This is already included in the H/W design files. When you program the "time-limited" SOF in Quartus Programmer, are you able to successfully program the configuration into the FPGA over JTAG? Does the Opencore IP Evaluation popup open and say "Time Remaining: Unlimited"?
