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ok i get this message every time i try to run the programm
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Certainly unusual. If I didn't know better, would say this is a timing issue, but as long as you are using the SOF file in the Quartus directory you shouldn't be having any trouble. Program memory is set to the SDRAM chip which requires a PLL to compensate for clock skew (approx -3ns shift). This is already included in the H/W design files.
When you program the "time-limited" SOF in Quartus Programmer, are you able to successfully program the configuration into the FPGA over JTAG? Does the Opencore IP Evaluation popup open and say "Time Remaining: Unlimited"?
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