Regarding SD RAM controller IN DE2

If you want the university program signals I can't help as I never got it to work, however, SRAM signals are pretty easy to understand, check the data sheet that same with the board and you can either control it with PIO signals if you're using Nios. Understanding the signals also lets you control flow in hardware if needed.

From my understanding (as it is probably not yet complete) control goes as follows:

There are control signals, all active low

ce_n : Chip Enable

we_n : Write Enable

oe_n : Read Enable

ub_n: Upper Byte Enable

lb_n : Lower Byte Enable

As well as data lines:

dq : Data Line(s)

addr: Address Line(s)

There are three main states I use:

idle

Control Lines high (ce_n, we_n, oe_n, ub_n, lb_n)

writing to sram

1. Put desired Address on addr lines

2. Put desired data on dq lines

3. Drop desired bytes (ub_n, lb_n) followed by chip enable and write enable (ce_n, we_n)

4. Wait for data to latch (check data sheet for timing, my clock rate is slower than the latch time so I skip this step)

5. Raise control signals

reading is similar

1. Put Address on addr lines

2. Drop desired bytes (ub_n, lb_n) followed by chip enable and read enable (ce_n, oe_n)

3. Wait for data to be available on dq lines (see step 4 above)

4. Obtain the data (data = dq)

5. Raise control signals

With the waveforms in the datasheet you should be able to determine which signals to use for which control on the SRAM, or write your own library, maybe even get the UP core working if that's you goal.You're also responsible for controlling data to and from the DQ line as it's bidirectional. This was a source of confusion at first for me. Hope this helps!