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It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding.
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thank you, It is really divided by 4, I have misunderstood because of the name CLOCK_2.
Therefore the MCLK is 12.5 Mhz ~ 12.288 Mhz. It is clear now.
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Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit.
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yes, in the demonstation, they set BOSR =0.
ROM= 16'h1000; //mclk
so, for the sample rate of 44.1 khz, i need to divide 50 mhz by 3 ( 16.667 mhz ~ 16.9344 mhz ) and set bosr = 1 ? --- Quote Start ---
Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value.
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Thank you for your suggestion.
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