Question about sample rate of audio codec WM8731 on DE2

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But the demonstration provides the clock of 25 Mhz ( 50/2 AUD_XCK pin).

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It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding.

Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit.

Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value.