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MReha2's avatar
MReha2
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6 years ago

Quartus Project for DEC10_Standard_Computer?

I am a professor for a US Canyon University and designing an Embedded Systems I and II class. I am using the DE10-Standard board for these classes. I downloaded the DE10-Standard Linux SD Card Imag...
AR_A_Intel's avatar
AR_A_Intel
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6 years ago
Hello Welcome to INTEL forum. For any question/request regarding University Program, drop an Email to psg.university@intel.com Our university team will help and answer your question.
MReha2's avatar
MReha2
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6 years ago

I FTP'd the Monitor Program using FileZile by downloading the intel_fpga_upds_setup.exe at ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/18.1/.

I then navigated to University_Program\Computer_Systems\DE10-Standar\verilog directory and opened up the Quartus project.

When I synthesize the file I get the following compiler error:

Error (12006): Node instance "edge_detection_router_controller" instantiates undefined entity "Computer_System_Video_In_Subsystem_Video_In_Edge_Detection_Subsystem_Edge_Detection_Router_Controller". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

I was expecting this to compile and work because I made not changes to the system.

Do you know how to resolve this error?