Quartus Prime Lite 20.1 University Program VWF simulation error
I am attempting to simulate a project for a MAX10 University Board using the University Program VWF simulator. The .vwf file was created from a project built with simple logic gates using block diagram file. The project compiles and the analysis and synthesis is complete. When creating the University VWF file, the nodes are identified and suitable stimulus is applied. The file is saved. When the functional simulation runs, the simulation flow progress shows that the EDA NetList writer was successful, and that the ModelSim.do script completed successfully. The simulation runs (with a warning that a VHDL design unit will be overwritten with a Verilog module but no errors). When the compiler begins to run, an error is written that reads
#**Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt option is now depracated and will be removed in future releases.
#Error loading design
No output results from this. If I edit the line below in the simulation options screen
#vsim -novopt -c -t 1ps -l fiftyfivenm,_ver -L a;tera_ver -L altera_mf_ver -l 220model_ver -L sgate_ver -: a;tera_lnsim_ver work.newone_vlg_vec_tst
to remove the -novopt text, to wit:
#vsim -c -t 1ps -l fiftyfivenm,_ver -L a;tera_ver -L altera_mf_ver -l 220model_ver -L sgate_ver -: a;tera_lnsim_ver work.newone_vlg_vec_tst
The simulation runs. Is there a configuration that I can change so that these settings don't have to be changed every time a simulation is run? Is this present in V20.2 if that is a "later version"? I don't recall seeing this error in V18.0
Thanks,
Bob
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