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Altera_Forum's avatar
Altera_Forum
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16 years ago

Quartus 9.1sp2 + University SD card core

Hi, I've been trying to build a rather basic computer for a DE1 board. This computer is basically the exact same as a DE1 basic computer but I need to add an MMU and support for the SD car...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

OK, I solved the problem. I generated the faulty component with version 9.1sp2 and tried to generate the project again in SOPC Builder - it DIDN'T work. Obviously , the SOPC Builder has a bug which doesn't allow to use two reset inputs in clock_sink component, where one is aclr (DSP Builder clock default) and second is a simple reset input.

Therefore I modified the appropriate vhdl interface in order to use only one reset input. This allows to generate SOPC Builder project. It doesn't solve the bug but allows me to move forward.

Regards