Quartus <--> Nios

This could help you:

http://www1.cs.columbia.edu/~sedwards/classes/2007/4840/lab3.pdf

http://www1.cs.columbia.edu/~sedwards/classes/2007/4840/lab3.tar.gz

The easiest way is to use a PIO peripheral in SoPC builder. Connect it to your NIOS. Then outside SoPC builder, connect the ports of the PIO to the signal you want to read. Then you can read the signal in NIOS using SoPC builder. By the way, the Simple Socket Server example does something similar except it reads rather than writes.

Jake

Thanks a lot. So from what I can understand, I should add tristate bridges (PIO) or a memory to the SOPC design, then connect necessary inputs in Quartus project, and finally use the base addresses to access the components from Nios program. Is that right? If so, how to use addressing in SDRAM, for example? In fact I would prefer using PIOs, but I'm not sure how many tristate bridges (if these are the ones I should use) I can add (I have about 40 bits that I have to send over the Ethernet frame).

I hope you can also help me with that. Thank you in advance.

cheers,

Adam

Ok, maybe I should be more specific.

I really like the idea of using PIO peripherals. From what I understand I should use tir-state bridges. My problem is, however, that it is impossible to assign specific base addresses to them in SOPC (as they use Flash memory). Does anybody know how I can access them in NIOS?

I would really apprieciate any help.

cheers,

Adam

The PIO peripheral connects directly to the NIOS data master bus. Don't use a tristate bridge.

Jake

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Let's say I have an output signal defined in a project in Quartus and I want to send the state of the signal using a C program in Nios. Can I somehow assign the signal to some address (or maybe some specific component, defined in SOPC Builder), so that I will be able to read it using a C program in Nios?

Adam

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Hi Adam,

You can easily implement this by opting for custom component in the SOPC Builder. You can make a new component wherein you can specify the read, read enable, clock, address and data signals for this component. You need not specify any HDL model here. This creates a "component" which is just a simple interface between NIOS and the rest of the HDL design. Here, you don't need any tri-state interface either.

Further, you can also have an Interrupt signal in this interface which is driven by a line that signals you that the state of the signal is up to be read.

I hope that helps.