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Honored Contributor
Honored ContributorProgramming Fail De0 board
Could anyone provide me some insight into why this continues to happen? I setup a block diagram file with this logic: AB'CD'+A'BCD. I have four inputs mapped to the correct pins for the first ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have a Timing warning shows up in red: All of my input ports and output ports are "unconstrained". Does this need to be corrected, even though I successfully compiled? --- Quote End --- Won't matter for this design, you can safely ignore the warning. It comes because you did not define any timing constraints on any of the I/Os, so Quartus is warning you of that. It will go ahead anyway and map the logic to the device, but it won't try very hard to improve the timing, since you provided no constraints. Most likely it is way faster than what you can do with your manual switches anyway.
