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Altera_Forum
Honored Contributor
15 years agoproblems with data passing in WM8731
Hye everyone .:) I have problems with passing the data from ADCDAT to my processing block. The mode set for the audio chip is left justified, 16 bit data width, 48Khz deemphesizes and 384 fs overs...
Altera_Forum
Honored Contributor
14 years agoQuartus 10 is good. so u r using 2 wire mode program.. hmm, did u set csb to the ground? or is that PUSHB[1] represent the csb itself?
Here is one thing, I dont use slave mode because in this mode , u r going to need to take care of the clock very well. I tried before, but, in the end I would prefer to choose master mode since i do not need to create clock divider to distribute the clock rate from AUD_XCK. One less problem there. I dont see any problems regarding about your I2C data. It seems good. I ll need to look again at my project, its been long(almost a year) because recently I am doing layout design. =="... by the way, check ur pin assignment carefully before you download it into the FPGA.