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ELupo's avatar
ELupo
Icon for New Contributor rankNew Contributor
6 years ago

Problems simulating ADC in DE10-Lite board using Quartus Prime Lite Edition in VHDL designs, and at gate level in verilog designs

Our course is actually based in DE0 Cyclone III board and VHDL using an old version of Quartus II. We are analyzing to move to DE10-Lite board and VHDL using Quartus Prime Lite Edition. We consider ...
Isaac_V_Intel's avatar
Isaac_V_Intel
Icon for Contributor rankContributor
6 years ago

Thank you for the feedback regarding the tool. We appreciate it.

I will work these bugs with engineering and try to solve that on future versions.

I believe the responses, in this case, have addressed your questions, if not feel free to post an update anytime during the close-pending period.

Best regards.