Problems simulating ADC in DE10-Lite board using Quartus Prime Lite Edition in VHDL designs, and at gate level in verilog designs

Thank you very much Isaac for your answer.

Yes. It is the same problem, but now it has been solved. In solving it, I have detected three bugs in, at least, version 19.1 of Quartus Prime Lite software, when you try to simulate the ADC in MAX10 FPGA family. I will report these three bugs later in this message.

I already had ModelSim-Intel FPGA Starter Edition installed, but I though that it was not a mixed VHDL/verilog simulator and I tried to simulate a full VHDL design. My VHDL design is named prova_ADC and my modular ADC core Intel FPGA IP variation is named nucli_ADC1.

WHAT IT WORKS

RTL simulation works well if you generate the modular ADC core IP in verilog. To aid in the explanation of bugs described below, it follows the content of file .../nucli_ADC1/simulation/submodules/nucli_ADC1_modular_adc_0.v, which consists in an appropriately parameterized instance of module altera_modular_adc_control:

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WHAT DOES NOT WORK (BUG 1)

RTL simulation does not work if you generate the modular ADC core IP in VHDL. The problem here is that Quartus Prime Lite generates file .../nucli_ADC1/simulation/sumodules/nucli_ADC1_modular_adc_0.vhd as an instance of an unknown non-parameterized component named nucli_ADC1_modular_adc_0_control_internal instead of an appropriately parameterized instance of the component named altera_modular_adc_control, as in the verilog case. It follows the content of the generated file:

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RTL simulation works well if you modify the content of file .../nucli_ADC1/simulation/submodules/nucli_ADC1_modular_adc_0.vhd to the correct one that is, an appropriately parameterized instance of the component named altera_modular_adc_control:

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WHAT DOES NOT WORK (BUG 2)

Gate level simulation does not work if you generate the compiled design in VHDL, described in file .../simulation/modelsim/prova_ADC.vho. The problem here is that Quartus Prime Lite generates an instance of the parameterized component fiftyfivenm_adcblock unassigning some generic parameters (enable_usr_sim, reference_voltage_sim, and simfilename_chx) and a port (clk_dft), and wrongly assigning another generic parameter (upper case letter must be used in device_partname_fivechar_prefix). It follows the relevant part of the content of the generated file .../simulation/modelsim/prova_ADC.vho:

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Gate level simulation works well if you modify the file .../simulation/modelsim/prova_ADC.vho to include an instance of the parameterized component fiftyfivenm_adcblock with all generic parameters and ports correctly assigned:

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WHAT DOES NOT WORK (BUG 3)

Gate level simulation does not work if you generate the compiled design in verilog, described in file .../simulation/modelsim/prova_ADC.vo. The problem here is that Quartus Prime Lite generates an instance of the parameterized module fiftyfivenm_adcblock unassigning some parameters (enable_usr_sim, reference_voltage_sim, and simfilename_chx) and a port (clk_dft), and wrongly assigning another parameter (upper case letter must be used in device_partname_fivechar_prefix). It follows the relevant part of the content of the generated file .../simulation/modelsim/prova_ADC.vo:

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Gate level simulation works well if you modify the file .../simulation/modelsim/prova_ADC.vo to include an instance of the parameterized module fiftyfivenm_adcblock with all parameters and ports correctly assigned:

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Please, try to correct these bugs in future versions of Quartus Prime. Thank you very much.

Best regards,

Emili Lupon