Honored Contributor
Honored ContributorI'm thinking that it may best to take the verilog example and re-construct it to be faster. The reason is i'm afraid that the uni cores will restrict the manipulations of the data too much. As in having to scale down to the format acceptable by those cores, but they might be that restrictive for a reason.
From the SOPC perspective the FIFO does work as I have done the earlier Uni core examples and customised them so they would work on the DE2-115. I rebuilt the SOPCs with the DE2-115 modules and took the software into a Nios project for examples 1, 2 and 3. I think the issue is possibly the AV core, i never noticed that the camera model number was different until i saw your post. I'm goig to look at the verilog example and try understand it, i may even try to modularise it for a schematic build or SOPC (but i got no idea about SOPC component creation). Also check to ensure you changed the clocks to their appropriate ones based on the Example 4 of the uni program cores.
