so you mean every time when you compile/configure your design, you acutally run up the whole FPGA resources in the device. I think it will explain why i have such funny results.
I simulate my design with a waveform in about 5ms, then the generated saf file is used to check the power with PowerPlay Analyzer. That is what i got about 28mW as the dynamic power. do you have any comments in my operation?
i really need your help to figure out the problems in my way to analyze the power of my design since my paper is due on Dec. 05.
Thanks.