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HighBaudUartEnjoyer's avatar
HighBaudUartEnjoyer
Icon for New Contributor rankNew Contributor
2 years ago

Porting QSYS Project with a modified UART Core to be able to compile on a licensed server

I am using the DE10-LITE FPGA to send a video stream from a camera to an ESP32 over UART for a university project. The maximum selectable baud rate of 115200bps on the AVALON UART IP CORE was severel...
University Program
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Is there any way I could build the .QSYS once on my laptop and then only compile a .pof on the university computer without regenerating the QSYS system.

  • I believe there is a disable button in setting for regenerating IP during compilation. You may try to disable it in licensed machine, load the modified design and compile with pof.