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In theory this would result in a 1000 MHz clock. It will however be very difficult to make circuits work at this high speed. You will definitly only have very small circuits and need to use the TimeQuest timing analyzer.
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It's not
difficult rather than simply
impossible. Apart from maximum I/O and internal register toggle rates, Cylone II has a maximum PLL output frequency of 500 MHz (in fastest -6 speed grade). You're correct however regarding the relation of clock rate and design complexity. In the Cyclone II Hardware Handbook, maximum clock rates for typical design entities are listed, e.g. counters or FIR filters under
timing specifications /performance.
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